The present invention relates to complementary metal oxide semiconductor (CMOS), and more specifically, to methods and structures to nanosheet devices.
CMOS is used for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS designs may use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
As CMOS scales to smaller dimensions, nanosheet devices provide advantages. Stacked nanosheets provide area efficiency. Stacked sheets also provide increased drive current within a given layout area.